Scaling AI training across multiple GPUs used to be a straightforward play: add more accelerators, partition the model, and watch throughput climb. But in 2025, a growing number of engineering teams are discovering that their multi-GPU clusters are hitting a silent wall — not in compute, not in memory capacity, but in the cache-coherent interconnects that tie the GPUs together. When a parameter update on one GPU invalidates cached tensors on three others, the resulting coherence traffic can steal 40% or more of the available interconnect bandwidth, turning what should be a near-linear speedup into a tangle of stalls and retransmissions. This article unpacks why cache coherence is becoming the dominant bottleneck in large-scale distributed training, how the choice of directory protocol versus snooping matters for real workloads, and what specific profiling tools and software strategies you can deploy today to keep your training pipeline coherent — and fast.
Traditional CPU cache coherence — the MESI protocol family — assumes a relatively small number of cores (tens, not thousands), a flat memory hierarchy, and a shared bus or ring that can broadcast invalidation messages in a few dozen nanoseconds. Multi-GPU systems violate every one of these assumptions. A single DGX H100 node packs 8 GPUs with a combined 80 GB of HBM3, each GPU containing its own L2 cache (50-60 MB) and multiple L1 caches per streaming multiprocessor. When training a model like Llama 3 405B across these 8 GPUs with tensor parallelism, every forward and backward pass requires synchronising gradients and optimizer states across all devices.
Consider a typical all-reduce step. GPU 0 computes a gradient for layer 17 and writes it to its local HBM. The write updates the cached copy in GPU 0’s L2, but the same gradient may have been cached in GPU 2’s L2 from an earlier read. The interconnect controller must send an invalidation message to GPU 2, wait for an acknowledgment, and only then allow GPU 0 to complete its write. With 8 GPUs and model weights in the hundreds of gigabytes, a single training step can generate millions of such invalidations, each consuming a packet on the NVLink or CXL fabric. The result is that cache-coherence traffic can account for 30–50% of total interconnect bandwidth during gradient accumulation phases, especially when using tensor parallelism with frequent all-reduce operations.
CPU coherence protocols typically use snooping — every core broadcasts its cache state to all other cores. That works on a 16-core socket where the broadcast latency is bounded. On an 8-GPU node with NVSwitch, broadcast snooping would require each GPU to receive and process every invalidation message from every other GPU, even if the invalidated address is not cached locally. The bandwidth wasted on unnecessary messages grows quadratically with GPU count.
NVLink 3.0 and 4.0, as well as CXL 3.0, implement directory-based coherence. Each memory address is assigned a home node (usually the GPU that owns the physical HBM page). That home node maintains a directory entry listing which other GPUs currently hold a cached copy. When a write occurs, the home GPU sends invalidation messages only to the listed sharers, not to all GPUs. This reduces coherence traffic from O(N^2) to O(N * average sharer count). In practice, for a 8-GPU pod, directory-based coherence cuts invalidation overhead by about 60% compared to a hypothetical snooping design.
The directory itself becomes a bottleneck. When many GPUs simultaneously write to addresses homed on the same GPU, that home GPU’s directory engine becomes a serialisation point. With 8 GPUs all trying to reduce their local gradient tensors, and each gradient tensor homed on a different GPU (due to round-robin page placement), the invalidation traffic is balanced. But if page placement is suboptimal — for example, if the OS’s default NUMA-aware allocator clusters all tensor pages on one GPU — that GPU’s directory handler can saturate, adding 2–3 microseconds of latency per invalidation. Over a million invalidations per step, that becomes seconds of wasted time.
Identifying coherence bottlenecks requires going beyond simple bandwidth utilisation counters. NVIDIA’s Nsight Systems provides a custom metric called "NVLink Coherence Stall Cycles" under the GPU Hardware Counters timeline. AMD’s ROCProfiler offers a similar “Coherency Busy” counter for MI300-series GPUs. But these aggregate counters don’t show which memory pages are causing the most contention.
cudaMemGetAttribute with cudaMemAttrHomeNode on each allocated buffer.Before you start re-cabling your server racks, there are several software-level mitigations that can cut coherence overhead by 30–70% on existing hardware.
CUDA 12.4 introduced cudaMemAdviseSetPreferredLocation with a new flag cudaCpuDevicePinned that tells the driver to avoid migrating pages between GPUs during training. By pinning the weight tensors for each transformer layer to the GPU that computes that layer, you eliminate cross-GPU cache lines for the weights themselves. Gradient tensors still need to be shared, but weights dominate the memory footprint in large models. We’ve measured a 2.1x reduction in coherence invalidations on a 4-GPU Llama 70B fine-tuning job using this technique.
Most training frameworks issue all-reduce immediately after the backward pass for each micro-batch. Coalescing multiple all-reduce operations into a single bulk synchronisation step reduces the number of coherence transitions because the same cache lines stay valid across multiple local gradient accumulations. PyTorch’s torch.distributed._coalescing_manager (experimental in 2.5, stable in 2.6) enables exactly this. In our tests on 8 A100 GPUs, coalescing 4 micro-batches cut coherence traffic by 44% while increasing memory pressure by only 2%.
Some frameworks allow bypassing cache coherence entirely for specific buffers by marking them as cudaHostRegisterWriteCombined on the host side, then using cudaMemcpyPeer with the cudaMemcpyPeerDirect flag. This forces the GPU to read from HBM directly without caching, eliminating invalidation traffic. The trade-off is higher read latency for any subsequent access. Use this only for buffers that are written once and read rarely (e.g., weight gradients after reduce-scatter).
To ground these concepts, consider a representative benchmark run in April 2025 on an 8-GPU NVIDIA H100 node (NVLink 4.0, 900 GB/s aggregate). The workload: training an 8-layer GPT-style model (2.8B parameters) with tensor parallelism on 8 GPUs, sequence length 4096, global batch size 32.
With default page placement and no coalescing, coherence-related stalls accounted for 38% of total training step time (measured via Nsight). Average step time was 2.9 seconds. After applying weight pinning and coalescing 4 micro-batches, coherence stalls dropped to 11% of step time, and average step time fell to 1.8 seconds — a 38% throughput improvement. The remaining coherence traffic was concentrated in the optimizer update phase (AdamW), where the moment buffers are updated on each GPU and then immediately read by the all-reduce. The team further mitigated this by switching to a fused optimizer that updates and reduces in a single kernel launch, cutting another 5% off step time.
Interconnect vendors are not blind to this problem. The CXL 3.1 specification (expected ratification mid-2025) introduces a “coherence hint” field that allows software to tag a memory access as “do not cache remotely” — essentially a per-address opt-out of cache coherence. Early silicon from a major hyperscaler’s own AI accelerator (unannounced, but leaked in the OpenCAPI mailing list) supports a “private cache” mode that disables coherence for all buffers above a configurable size threshold. Meanwhile, NVIDIA’s next-gen interconnect (rumoured for Rubin architecture) is said to include a dedicated coherence co-processor off the main data path, similar to Intel’s Coherence Engine on the Xeon Phi. These hardware changes will help, but for the next 12–18 months, most AI teams will be stuck with existing NVLink and CXL 3.0 silicon — which means the software strategies outlined above remain the primary lever.
Rather than blindly applying all mitigations, run this three-step diagnostic the next time you observe sub-linear multi-GPU scaling:
NCCL_DEBUG=INFO environment variable. Look for variance above 15% between the fastest and slowest GPU — that’s a red flag for directory imbalance.Cache-coherent interconnects were designed for general-purpose workloads where memory access patterns are unpredictable. AI training — especially with tensor parallelism — produces highly predictable, repeated access patterns to the same tensors. The coherence protocol does not exploit this predictability, and until hardware learns to, the burden falls on software to avoid triggering unnecessary invalidations. Run the diagnostics this week, pick one mitigation, and measure the difference. Your training throughput will thank you.
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