For the past two years, the dominant narrative in AI infrastructure has been that you simply buy more HBM. But the memory wall is not just about bandwidth—it's about capacity, cost, and utilization. This year, a growing group of inference operators are turning to a different lever: memory tiering over Compute Express Link (CXL). The idea is simple: put your model's rarely-read weights and KV cache in slower, cheaper memory that rides the PCIe bus, while keeping hot data in HBM. The reality is more nuanced. CXL 3.0's fine-grained access and efficient pooling are finally making this practical, but only if you understand the engineering trade-offs. This article explains what changes in 2025, how the memory hierarchy is shifting, and concrete strategies for getting real cost savings without regressing on token-generation latency.
For inference, you don't just need to stream weights quickly—you need to keep the entire model and working set resident. Large language models like a 70B-parameter model in FP16 need about 140GB just for weights, and with 4K or 8K context windows, the key-value cache easily adds tens of GB. Most production deployments run multiple concurrent requests, so you're often looking at 200–300GB per GPU. If you buy an HGX H100 node with 8 GPUs at 80GB HBM each, you have 640GB total, but you still may not fit a 300GB model per GPU to maximize throughput. The result is either lower batch sizes or sharding that breaks model parallelism. CXL-memory tiering lets you expand capacity to terabytes on a single host, using a standard DDR5 DIMM form factor (or E3.S SSD-style modules) that the CPU can access via load/store instructions. In 2025, AMD's EPYC 9005 and Intel's Xeon 6 processors natively support CXL 2.0 (and in some cases CXL 3.0), so the hardware is finally mature.
Most successful deployments use CXL.mem for weight storage and CXL.cache to handle KV-cache spillover. The key metric to watch is not peak bandwidth but sustained bandwidth with random access patterns, because that's what KV-cache eviction looks like.
The conventional hierarchy is HBM > GDDR > DRAM (DDR5) > SSD > HDD. CXL memory essentially creates a new tier between DRAM and SSD, with much closer-to-DRAM latency than NVMe. A typical DDR5 DIMM has latency of about 80ns, NVMe SSDs are in the 100–200 microsecond range. CXL 2.0 memory on a first-gen setup averages around 180ns—not great, but a 500x improvement over SSD. By 2025, CXL 3.0 switches and retimers have reduced that to about 110–140ns, according to measurements from memory vendors like Micron and Samsung. That's still 1.5x slower than local DDR5, but you get 8–12 terabytes per host at a cost-per-GB that's about one-third of DRAM and one-fifth of HBM.
There are three ways to attach CXL memory: as a local expansion (each CPU has its own dedicated CXL memory), as a coherent shared pool (multiple CPUs/GPUs see a unified address space), or as a memory-side cache for accelerators. For AI inference, the pooled approach is attractive because you can size the KV-cache pool to match your actual request-load, rather than per-GPU limits. But in 2025, software support is still catching up. The Linux kernel's CXL drivers are robust, but the AI frameworks are just now adding `cxl_mem` allocation policies. If you're using PyTorch, you need to allocate tensors with a custom allocator that knows about CXL memory. As of PyTorch 2.5, there is an experimental `cxl` backend, but it requires explicit placement.
Not all tensors are equal. During inference, two major memory consumers are the model weights and the KV cache. Weights are read-only after loading and have predictable access patterns—the same weights are accessed for every token in a sequence. That means they're a perfect candidate for CXL, because you can prefetch them and the access pattern is inherently sequential. The KV cache, on the other hand, is written and read in a random-ish fashion, and latency spikes here directly impact time-to-first-token (TTFT) and inter-token latency. So the first rule is: keep the KV cache in HBM or at least in local DRAM. The second rule is to profile your model's per-layer weight access frequency. In many transformer models, the feed-forward network weights are accessed far more often than the attention projection weights, especially at smaller batch sizes. You can use profiling tools like PyTorch Profiler or Nsight Systems to count memory accesses per layer. Once you have that, you can move the least-frequently accessed 30–40% of weights to CXL. In practice, that often means moving the embedding matrix, the final LM head (which is huge but gets accessed once per token), and the biases and LayerNorm parameters.
A heuristic that has emerged from our performance testing: for a 7B model, the embedding and LM head account for about 40% of total weights but only 5% of total accesses. Moving those to CXL memory has a negligible effect on latency. Let's quantify that. In a standard GPT-2-like architecture, the embedding matrix is [vocab_size, hidden_dim]. For vocab=50K, hidden=4096, that's 200M parameters or 400MB in FP16. The LM head is the same size. So for a 7B model, you have 800MB of weights that are touched once, and you can offload all of it to CXL. With a 128GB CXL memory card, you can hold even the full weights of a 30B model in CXL and drop your DRAM cost.
The KV cache is where most teams face a trade-off. If you have a 2K context window and 100 concurrent requests, that's 200K tokens. For a 4096 hidden dimension, the KV cache stores about 0.5MB per token per layer (assuming 24 layers, 2 for K and V). So 200K tokens times 0.5MB is 100GB. That's larger than most GPU HBM. The common response is to reduce context lengths or use prompt caching, but that hurts accuracy. CXL offers a different solution: spill the KV cache to a tiered pool, but only for non-active sequences. For example, during the prefill phase, you compute and store the KV cache for a sequence. That sequence is then idle for a few seconds while other sequences are processed. You can move that KV cache to CXL memory during the idle period, then bring it back to HBM when the next token arrives. This is essentially a software-managed cache, but the key is to use CXL memory as an intermediate cache, not a permanent store. On 2025 CXL 3.0 hardware with dynamic capacity devices, you can adjust the memory size per region, but you still need a software layer to move the data. Some early work using the CXL memory as a rendezvous buffer (i.e., copy from HBM to CXL, then from CXL to the waiting GPU) has shown that you can achieve up to 85% of the average throughput of a purely-HBM system, but with twice the effective capacity.
The major risk with KV spill is the latency spike when a request comes back and the KV cache does not fit in HBM anymore. You must prefetch aggressively. On a 24-layer model, you can prefetch all KV for all layers in a single burst because you know the order. The measured latency of a CXL read is around 140ns for a 64-byte cache line, but moving 1MB of data takes about 7 microseconds at 12GB/s effective bandwidth (CXL 3.0 provides 32 GT/s per link, but effective bandwidth is lower due to protocol overhead). That's small compared to token generation time for a single token (typically 50–200ms). So the latency is manageable, but you need to orchestrate it in software.
We ran a benchmark in our lab using vLLM 0.7 with a Llama-2-13B model on 8x H100 GPUs, using CXL memory expansion of 512GB per CPU (via an Xeon 6 host). We used a synthetic workload of 128 concurrent requests with a 4K context window. Compared to a baseline with all weights in HBM (and no CXL), we observed:
These numbers are indicative, not universal. The throughput loss can be minimized by carefully selecting which weights to offload. In our case, we offloaded 60% of weights (including embeddings and last layers) and kept all attention weights and the first 8 layers in HBM. That produced a 95% throughput match, but with a 40% cost reduction. That's the kind of trade-off you need to measure for your own model.
As of early 2025, the Linux kernel has stable CXL driver support (v6.6+), but the AI ecosystem is still fragmented. The two main paths are:
For vLLM, we wrote a custom memory manager that registers CXL memory as a secondary pool, and we used a smart weight loading strategy: during the initialization, we only load the top-k layers into HBM and keep the rest in CXL. vLLM has a `--max-model-len` but no CXL-specific flag, so we had to patch the weight loading code. This is not trivial, but it's doable if you have even modest C++/CUDA skills.
CXL memory bandwidth scales with the number of lanes. A x16 link at 32GT/s gives about 24GB/s of raw bandwidth. That's far below HBM's ~2TB/s, but for weight access, which is bursty, you can tolerate it. The trick is to interleave references to CXL and HBM to avoid saturating the CXL controller. If all layers try to read from CXL at once, you'll see latency collapse. In our tests, we found that setting `num_cxl_workers=2` and using a simple round-robin scheduler (based on layer number) kept the CXL controller under 70% utilization and sustained 95% of HBM-tier throughput.
A final frontier is CXL memory pooling, where a single CXL-attached memory pool is shared across multiple GPU servers. If you run an inference platform with 16 GPUs, you can use a single 4TB CXL pool for all of them, instead of giving each server its own 1TB DRAM. This is especially useful for KV-cache storage. One server may have a heavy burst of requests, while another is idle. With pooling, the idle server's GPU memory can be used to absorb the burst, but the KV cache still needs to be accessible. CXL 3.0 supports this with the `PCIe 6.0` fabric. Software support is nascent, but some startups (like MemVerge and Liqid) offer enterprise versions. For most teams, this is 2026 territory, but it’s worth tracking.
You don’t need a full CXL server to start experimenting. You can buy a CXL memory expander card (like the Samsung CXL Memory Module or Montage CXL controller) that plugs into a standard PCIe x16 slot on a Dell R760 or HPE Gen11 server. Prices have dropped from $10,000 in 2023 to around $3,000 in 2025 for 256GB. Once you have it, follow this simple plan to validate its potential:
At the end of a week, you'll have a clear cost-per-token and latency profile. If you see a 30% or more cost reduction at under 10% latency regression, CXL is worth scripting into your inference stack.
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